http://onsemi.com MARKING DIAGRAMS NBXDBA019 125/250 AWLYYWWG 6 PIN CLCC LN SUFFIX CASE 848AB
*
*
*
*
*
*
*
*
* LVPECL Differential.

The device uses a high Q fundamental crystal and Phase Lock Loop (PLL) multiplier to provide selectable 125 MHz or 250 .

LVTTL/LVCMOS Control Input LVTTL/LVCMOS Control Input Power Supply Output Enable Pin. When left floating pin defaults to logic HIGH and output is active. See OE pin description Table 2. FSEL/ NC* GND CLK CLK VDD Output Frequency Select Pin. Pin will .

Since 2006. D4U Semicon.   |   Contact Us   |   Privacy Policy   |   Purchase of parts